In frequency synthesis an accurate reference clock is used as basis for stability and accuracy. However such a clock generally has a fixed frequency. Therefore, fractional frequency synthesizers with analog PLLs (Phase Locked Loops) are used to generate a clock with the desired frequency. An analog PLL is usually used to multiply the frequency and a divider is used to divide the frequency.
There are many applications that require a very wide frequency spanning multiple decades from hundreds of MHz down to 1 Hz. Such a range is not feasible for the Voltage Controlled Oscillator (VCO) that is part of the analog PLL. Additionally to suppress jitter and noise the VCO frequency range should be limited to up most an octave. This makes the VCO frequency range relatively small. When the maximum VCO frequency is chosen to be the highest required frequency, the output frequency range of the synthesizer can be increased by the use of counters/dividers.
When the frequency synthesizer with its analog PLL and its dividers is implemented in a silicon chip the hardware is fixed and cannot be changed afterwards. This means that when an output clock is needed with frequency below the lower limit a new die is needed. An example for frequency synthesis can be found in U.S. Pat. No. 5,905,388.
Frequency synthesis systems make much use of counters and/or dividers in their designs. They are used to reduce the frequency of some clock generator or to count a sequence of states that can be decoded to produce a complex waveform. The fractional frequency synthesizer of FIG. 1 is an example of such a system. In such a system, the output frequency is given by the expression
      f    out    =                    Q        FB                              Q          in                ·                  Q          out                      ·          f      reference      
The schematics and designs of such counters and/or dividers can be found in any basic textbook on digital electronics. The counters can be designed either with a fixed division ratio or flexible with programmable division ratio between 1 and the maximum count value Qmax. The counting range or division ratio will be limited. When a larger division ratio is needed the counter design needs to be changed. This requires a hardware modification.
The architecture of a frequency synthesizer includes the following elements: A reference; an analog PLL; a counter, and a decoding circuit. The decoding circuits translates/decodes the counter state to an output value. The shape of the output value could be a 50% duty cycle clock, a frame pulse or any other complex repeating signal as shown in FIG. 2.
Counters and dividers have some inherent limitations that have nothing to do with the skill of the circuit designer or the nature of counters. Some of these limitations are:                The carry chain limits the maximum speed.        The parallel load circuit forms a load on the counter circuits and limits the maximum speed. After loading a new counter value the carry chain must be updated within a single clock cycle.        Reset circuits form also a load on the counter circuit although it might be less than the parallel load circuits.        The output counters of a fractional PLL, which are connected to the VCO, will run at high clock rates and thus consume much power. Consequently long divider chains (Qout is large) will consume a considerable amount of power.        The decoding logic for the programmed division ratio and the frames pulses also runs at the high frequency of the VCO clock. Thus power consumption is high. Power of 2 division is achieved by choosing the correct tap of the counter. Than there is no decoding logic thus the power consumption is limited.        Hardware determines the maximum division ratio and you cannot surpass that barrier. Factory test time is getting a problem when the counter chains are getting long. The counters cannot be included into the scan chain because the extra circuitry forms an extra load and would decrease the maximum usable clock frequency of the counters.        
The start up phenomena in the analog PLL and output counters will introduce input/output and output/output misalignment. At start up the output counters will enter an undefined state. When two or more analog PLLs are started, the analog PLLs will follow different trajectories to a locked state even when they use the same clock as reference. This is due to slightly different component values, different noise sources, and delay values. The number of generated clocks over the locking period will be different. Consequently the counters that are connected to different analog PLLs will have different states.
Switching over to another reference frequency during the operation will force the analog PLL to lock to a different frequency. During locking the relation with the input clock might be lost. The trajectory the analog PLL follows during the locking has random components and is for a part not predictable. This will result in misalignment of the output in relation with the input and the other outputs.
Signals and clocks coming from different output counters will have different phases and there is a significant output-output offset and uncertainty about the offset. This is an undesired phenomenon. Precise and defined relations between different output clocks are a hard requirement for frequency synthesizers. In telecom systems, for example, when the frame pulse occurs all clocks must have rising edges at that moment.
These problems are solved when all counters have a direct relation with the reference. The relations between the analog PLLs and the reference are already defined. The reference is directly connected to the input of the PLL. But the counters must be tied to the reference. The state of the counters must be enforced to defined values at prescribed moments.
Loading a counter with a defined value on a precise moment can be done two different ways. Either the counter can be loaded with a constant value, which is not necessarily zero. This is called reset. Or, the counter is loaded with a varying value this is called loading. In essence reset is a specific form of loading. Both methods have been used either stand alone or in combination.
When the frequencies of the output clocks are very different; in other words with a very low common frequency, the number of common moments suitable for reset is significantly reduced. When more than one FEC (Forward Error Correcting) ratio is present in a telecom system the common frequency is very low. This causes long startup times. It takes a long time before one can be certain that the outputs are properly aligned. This will also become a problem during factory testing. Reset is not a optimal solution.
Factory test time of silicon chips is expensive. The more test time is required, the more money is involved. Any fabricated chip must be tested before can be sold and used. As stated earlier scan chains can be used in output counters because of the high frequencies involved. Only functional testing is possible. When however a long divider chain is required the test time will become unacceptably large.